I have created a module for DFlipFlop in DFF module and instantiated 4 of them in seqgen module. I am not able to generate results. Can you please help me where I am going wrong?
module DFF(input d, input rstn, input clk, output reg q);
always @(posedge clk or negedge rstn)
if(!rstn)
q <= 0;
else
q <= d;
endmodule
module seqgen();
wire q1=1'b1,q2=1'b1,q3=1'b1,q4=1'b0;
wire da=1'b1;
reg clk = 1'b0,rstn = 1;
always #10 clk = ~clk;
assign da = ~q1|~q2|~q4;
DFF dffa(da,rstn,clk,q1);
DFF dffb(q1,rstn,clk,q2);
DFF dffc(q2,rstn,clk,q3);
DFF dffd(q3,rstn,clk,q4);
endmodule
There are 2 types of problems.
The outputs of your DFF modules are being driven from within the DFF module and from within the seqgen module due to the continuous wire assignment. You should not assign a value to the wire. This causes contention which is one source of the unknown values (x) on the outputs. In the case of da, you have 2 continuous assignments, but you should only have 1.
Also, you should assert the reset at time 0, wait for a delay, then deassert the reset. This is another source of the unknowns. Since it is an active-low reset, set it to 0, then after a delay, set it to 1.
This code gets rid of the unknown signals for me.
module seqgen();
wire q1,q2,q3,q4;
wire da;
reg clk = 1'b0, rstn = 0;
initial #25 rstn=1;
always #10 clk = ~clk;
assign da = ~q1|~q2|~q4;
DFF dffa(da,rstn,clk,q1);
DFF dffb(q1,rstn,clk,q2);
DFF dffc(q2,rstn,clk,q3);
DFF dffd(q3,rstn,clk,q4);
endmodule