how to estimation a chip size with standard cell library

I have recently started using yosys, synthesized a DSP block with cmos_cells.lib and got following results:

    ABC RESULTS:              NAND cells:     2579
    ABC RESULTS:               NOR cells:     2771
    ABC RESULTS:               NOT cells:      447
    ABC RESULTS:        internal signals:     3728
    ABC RESULTS:           input signals:      133
    ABC RESULTS:          output signals:      128 

I don't have access to commercial standard cell library at the moment, but I am trying to get an estimate of the die size for this design with, e.g., TSMC 28nm process.

I would appreciate if someone could help me with this

Thanks

There's no getting around needing a cell library for (roughly) the process you want. Once you have one, map to it and then run stat -liberty cells.lib to calculate total cell area.