What is this following syntax error in Verilog Icarus tool?

module alu(input [7:0] A,B,
       input [3:0] selector,
       output [7:0] ALU_output,
       output ALU_output_carry 
       );
reg [7:0] ALU_result;
wire [8:0] tmp;
assign ALU_result=ALU_output;
assign tmp={1'b0,A}+{1'b0,B};
assign ALU_output_carry= tmp[8];
always @(*) begin
case(selector)
4'b0000: ALU_result= A+B;
4'b0001: ALU_result=A-B;
4'b0010: ALU_result=A&B;
4'b0011:ALU_result=A|B;
default: ALU_result=A-B;
endcase
end
endmodule
           

Above is the Verilog code (I saved it by this name "8it_alu_code.v", without double quotes) for 8bit ALU, and following is it's testbench (I saved it by this name "8it_alu_tb.v", without double quotes).

`timescale 1ns/1ps
module alu_tb;
reg[7:0] A,B;
reg[3:0] selector;
wire[7:0] ALU_output;
wire ALU_output_carry;
integer i;
alu test(A , B , selector , ALU_output , ALU_output_carry )
initial begin
$dumpfile("dump.vcd");
$dumpvars(1,alu_tb);
A=8'b00000010;
B=8'b00000110;
selector=4'b0000;
for(i=0;i<4;i++)
begin
selector=selector+4'b0001;
#10
end
end
endmodule

When I am compiling it on the Icarus tool as follows:

iverilog -o 8it_alu_code.v 8it_alu_tb.v

I am getting this error (in testbench file I think)

8it_alu_tb.v:1: syntax error
I give up.

Then, I thought there could be some problem in simulator, so I went to 'EDAplayground' website and run both files in there online simulator. There I got following errors, without any output waveform or anything:

No top level modules, and no -s option.
Exit code expected: 0, received: 1

I want it to run successfully either on my 'ICARUS+GTKWAVE' and give some waveform output, or on EDA Playground online simulator. But, it is not compiling successfully. So, please kindly give some suggestions as what should I do to get rid of it.

You never drive ALU_output, and you have multiple drivers for ALU_result.

This line:

assign ALU_result=ALU_output;

should probably be changed to:

assign ALU_output=ALU_result;

iverilog currently does not support much of SystemVerilog. The ++ operator was introduced in SV. Change:

  for(i=0;i<4;i++)

to:

  for(i=0;i<4;i=i+1)

Two lines were missing semicolons (added below):

alu test(A , B , selector , ALU_output , ALU_output_carry );

#10;