This might be super basic but I didn't find any Info on this; if in Harvard Architecture Data and Instructions need to be accessed at the same time, does this require the CPU to have two distinct MAR's that point to their respective addresses and two that point to their respective Data? Or is this handled differently?
Yes, if the Harvard CPU has a simplistic non-pipelined bus interface that actually has a physical MAR and MDR (non-toy mainstream CPUs don't, but a simple microcontroller might have something at least equivalent).
In general yes there are two separate bus interfaces, if it's a true Harvard. Not just split caches in front of unified outer cache + memory, aka Modified Harvard.
That's part of the point of Harvard, allowing parallelism between code fetch and data load/store, avoid the von Neumann bottleneck. As well as having a separate address-space. (But of course even Harvard machines have to get data to/from memory to feed the ALUs with useful work.)