How to identify synchronous resets (in verilog)

I'm new to EDA and I have the following verilog code and i need to identify the synchronous reset clearly.

module test(clk,d,rst,a);
  input clk,d,rst;
  output reg a;

  always @(posedge clk)
  begin
    if(rst)
      a <= 1'b0;
    else
      a <= 1'b1; // assigned to a constant
  end
endmodule

is 'rst' a reset (synchonous) ?

The accepted answer is wrong, since the 2nd code sample is actually a Combinational code and doesn't use clock at all, we need to implement a Sequential code. The first code sample is a Synchronous Reset:

//Synchronous Reset
module test(clk,d,rst,a);
  input clk,d,rst;
  output reg a;

  always @(posedge clk) 
  begin
    if(rst) // In order to execute this line, clk and reset both have to be in posedge.  
      a <= 1'b0;
    else
      a <= 1'b1; // assigned to a constant
  end
endmodule

The second code sample is an Asynchronous Reset:

//Asynchronous Reset
module test(clk,d,rst,a);
  input clk,d,rst;
  output reg a;

  always @(posedge clk, posedge rst) 
  begin    
    if(rst) // In order to execute this line, rst has to be in posedge(clk's value doesn't
            // matter here, it can be either posedge or negedge, what's important is rst's value). 
      a <= 1'b0;
    else
      a <= 1'b1; // assigned to a constant
  end
endmodule