In the receiver side of the physical layer's logic block, the local clock is accurate to +/- 300 ppm. Can anyone explain about this in details please?!
The PCIe local clock is specified at 100MHz. In real life you never get an oscillator that is always perfectly at this frequency. The accuracy figure of 300ppm means that the "real" clock signal may vary between 99.97MHz an 100.03MHz but not beyond.