I have searched Intel manual Vol.4. MSR 0x1a4 can control L1 cache prefetcher and L2 cache prefetcher, but I just want to disable L3 cache prefetcher. Which MSR can control it?
There is no dedicated L3 prefetcher in current Intel processors. However, starting with Sandy Bridge, the L2 streaming prefetcher can choose to either prefetch into the L3 cache or the L2 cache. This is briefly discussed in the Intel Optimization Manual.
LLC prefetching can be disabled separately, but Intel has only disclosed how to do this to BIOS vendors. On a Xeon SP of any generation, there is a BIOS option called something like "LLC prefetch" that you can use to enable or disable LLC prefetching. If disabled, it may reduce the aggressiveness of the L2 streamer but it can still prefetch into the L2. As you may already know, Intel has disclosed how to fully disable any and all L1D and L2 prefetchers on all Intel x86 processors via MSR registers.
Other related prefetch mechanisms on Xeon SP include sending a prefetch request to a locally homed cacheable address if the access to the L3 is predicted to miss and similarly sending a prefetch request to a remotely homed (cross-socket in particular) cacheable location. These are useful because a significant fraction of an L2-miss access latency is spent on the L3 lookup operation for hit/miss determination. There are BIOS options to control these prefetching mechanisms as well. The exact names depend on the BIOS vendor. But note that prefeched lines in these cases bypass the L3 like what happens with any other core-originated request. Technically speaking, though, such prefetch requests are sent by the L3.
All prefetching mechanisms are normally enabled by default, except for LLC Prefetch, which may be disabled by default.