Test benching a 24 bit signal in an 8 bit component

I've been working on my homework assignment where we had to create a parity bit generator circuit that for an 8 bit sequence outputs a 9 bit sequence where the new is the parity bit (it get set to 1 if there is an odd number of bits that are 1 in the sequence). This is the code for it:

library ieee;
use ieee.std_logic_1164.all;

entity top is
      port( 
            idata:in bit_vector(7 downto 0);
            odata:out bit_vector(8 downto 0)
            );
end top;

architecture parity_gen of top is
signal temp : bit_vector(5 downto 0);

begin
    temp(0)<=idata(0) xor idata(1);
    temp(1)<=temp(0) xor idata(2);
    temp(2)<=temp(1) xor idata(3);
    temp(3)<=temp(2) xor idata(4);
    temp(4)<=temp(3) xor idata(5);
    temp(5)<=temp(4) xor idata(6);
    odata(0)<= temp(5) xor idata(7);
    odata(1)<=idata(0);
    odata(2)<=idata(1);
    odata(3)<=idata(2);
    odata(4)<=idata(3);
    odata(5)<=idata(4);
    odata(6)<=idata(5);
    odata(7)<=idata(6);
    odata(8)<=idata(7);
end parity_gen;

Now I also created a testbench program for it that looks like this:

library ieee;
use ieee.std_logic_1164.all;

entity top_tb is end top_tb;

architecture behavior of top_tb is
    component top is
        port( 
            idata:in bit_vector(7 downto 0);
            odata:out bit_vector(8 downto 0)
            );
    end component;
    signal input  : bit_vector(7 downto 0);
    signal output : bit_vector(8 downto 0);
begin
    uut: top port map (
        idata(7 downto 0) => input(7 downto 0),
        odata(8 downto 0) => output(8 downto 0)
    );

    stim_proc: process
    begin
        input <= "10100101"; wait for 10 ns; assert output = "101001010" report "test failed";
        report "Top testbench finished";
        wait;
    end process;
end;

Is there a way to test this component for a longer input sequence, lets say 24 bits and what actual changes would I have to make in the code to achieve that?

Input : [ 1 0 1 0 0 1 0 1     1 1 0 0 0 1 1 1    1 0 1 0 1 1 0 0  ]
Output: [ 1 0 1 0 0 1 0 1 0   1 1 0 0 0 1 1 1 1  1 0 1 0 1 1 0 0 0]

I basically want to do something like this:

input <= "101001011100011110101100"; wait for 10 ns; assert output = "101001010110001111101011000" report "test failed";

You can create a forloop and just iterate over elements of an array of inputs while checking a similarly sized array of outputs

type t_in_array is array 0 to num_of_inputs of std_logic_vector(7 downto 0);
  signal s_input_arr : t_in_array := ("10100101", ...); 
type t_out_array is array 0 to num_of_inputs of std_logic_vector(8 downto 0);
  signal s_exp_out_arr: t_out_array := ("101001010", ...);

stim_proc: process
begin
for i in 0 to num_of_inputs
  input <= s_input_arr(i);
  wait for 10 ns;
  assert output = s_exp_out_arr(i)
    report "failed";
end loop;
wait;
end process stim_proc;

Wrote that on the fly without testing FYI.