4-bit comparator issue in vhdl

I am new to VHDL and I have an issue writing a 4-bit comparator. When I want to compare different sets of inputs there is only one output for all of them. And I don't know how to solve this problem. I want to have only one output and need to show 0000 if A is less than B, and 1111 if A is greater than B, and 0011 if they are equal. Can anybody please help me with my problem?

Here is my code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comp_4 is
    port (  A:IN STD_LOGIC_VECTOR(3 downto 0);
            B:IN STD_LOGIC_VECTOR(3 downto 0);
            output:OUT STD_LOGIC_VECTOR(3 downto 0)
    );
end comp_4;
    
architecture dataflow of comp_4 is
begin
    process
    begin
        if (A=B) then
            output <= "0011";
        elsif (A>B) then
            output <= "1111";
        else
            output <= "0000";
        end if;
        wait;
    end process;
end dataflow;

And also my test bench:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Comparator_test IS
END Comparator_test;

ARCHITECTURE Ctest OF Comparator_test IS
    COMPONENT comp_4 IS
        port(   A:IN STD_LOGIC_VECTOR(3 downto 0);
                B:IN STD_LOGIC_VECTOR(3 downto 0);
                output:OUT STD_LOGIC_VECTOR(3 downto 0)
        );
    END COMPONENT;

    SIGNAL a : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL b : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL c : STD_LOGIC_VECTOR(3 downto 0);
BEGIN
    uut : comp_4 PORT MAP(a, b , c);
    a <= "0100" , "1111" After 10 NS;
    b <= "0101" , "1100" AFTER 10 NS;
END Ctest;

And my simulation looks like this:

You need to put the inputs on the sensitivity list.

Note, wait; stops the process infinitely (only in simulation, it cannot be synthesized).

Solution 1:

Use the process' sensitivity list, and remove wait;.

architecture dataflow of comp_4 is
begin
    process(A, B)
    begin
        if (A = B) then
            output <= "0011";
        elsif (A > B) then
            output <= "1111";
        else
            output <= "0000";
        end if;
    end process;
end dataflow;

Solution 2:

Use the sensitivity list of wait.

architecture dataflow of comp_4 is
begin
    process
    begin
        if (A = B) then
            output <= "0011";
        elsif (A > B) then
            output <= "1111";
        else
            output <= "0000";
        end if;
        wait on A, B;
    end process;
end dataflow;