system-verilogsystem-verilog-assertions

SystemVerilog disable cover property after hit

I have a few cover property's that I expect to fire pretty frequently, and I'm seeing they are starting to impact my simulation performance because they are firing so frequently. I don't want to remove them because I want to make sure I am still hitting these properties, but I don't care how many times I hit them. Is there a way to disable the cover property after it's hit once so it won't hinder simulation performance?

B2BReq : cover property ( 
  @(posedge CLK iff !RESET)
  Intf.ReqValid ##1 Intf.ReqValid
);

I'm thinking of something like this:

bit cov_disable;
B2BReq : cover property ( 
  @(posedge CLK iff !RESET) disable iff(cov_disable)
  Intf.ReqValid ##1 Intf.ReqValid |=> cov_disable = 1
);

But this is incorrect syntax. Is there a way to achieve something like this?

Solution

  • Some tools automatically disable a cover directive when it hits a certain limit. I know that in Questa, the default is disabling after 1 hit.

    Also, you may get better performance modeling what you want with a simple implication

    B2BReq : cover property ( 
  @(posedge CLK iff !RESET)
  Intf.ReqValid |-> ##1 Intf.ReqValid;
);

    BTW, the syntax you were looking for was

    bit cov_disable;
B2BReq : cover property ( 
  @(posedge CLK iff !RESET) disable iff(cov_disable)
  Intf.ReqValid ##1 Intf.ReqValid |=> (1,cov_disable = 1);
);