Error: (E107) bind interface to port failed: type mismatch on port 4 of module `simple_instance.data_in_reg'

i want to read bus in register_out and write to bus in register_in but i get type mismatch error on port4 of register_in

Register.hpp file

#pragma once
#include<systemc.h>
#include"bus.hpp"
class Register:public sc_module{
private:
  sc_port<sc_signal_in_if<sc_logic>> clk,rst,lden;
  sc_port<sc_signal_in_if<sc_lv<8>>> in_load;
  sc_port<sc_signal_write_if<sc_lv<8>>> out;

public:
  SC_CTOR(Register){
    SC_METHOD(eval);
    sensitive<<clk<<rst;
  }
void eval(){
    if(rst->read()=='1')
        out->write(0);
    else if(clk->event() && clk->read()=='1')
        out->write(in_load->read());
  }
};

test_module head file

#pragma once  
#include<systemc.h>
#include"Register.hpp"
class test_module:public sc_module{
  sc_port<sc_signal_in_if<sc_logic>> clk,rst,lden_in,lden_out;
  sc_port<sc_signal_in_if<sc_lv<8>>> data_in;
  sc_port<sc_signal_write_if<sc_lv<8>>> data_out;
  sc_port<sc_signal_inout_if<sc_lv<8>>> bus; 

public:
  Register  *data_in_reg,*data_out_reg;
  SC_CTOR(test_module){
    data_in_reg=new Register("data_in_reg");
      (*data_in_reg)(clk,rst,lden_in,data_in,bus); // ERROR  
    data_out_reg=new Register("data_out_reg");
      (*data_out_reg)(clk,rst,lden_out,bus,data_out);
   }
 };

i replace sc_port<sc_signal_in_if> to sc_in and sc_port<sc_signal_write_if> to sc_out and make bus to sc_inout and it's work. but i have question why this way work but by using sc_port and interface i got mismatch error