recomend the way to write a monitor in UVM with defferent event polarity

I am trying to implement a monitor for VDU(Video display unit) and the way the VDU can be programmed says that sync signals have controllable polarity. This means than according to VDU settings monitor should react on @posedge or @negedge event. Is there any way to pass the type (means posesge or negedge) via configuration data base or do something like this. Instead of write if(truth) @posedge else @negedge. And assertion also needs to be controlled this way but assertion at list designed to take event type as an argument but I am no sure config data base calls are allowed inside interface.

You should write your code assuming positive polarity, but feed them through an xor operator.

logic signal;           // your signal from DUT
logic signal_corrected; // signal with positive polarity
bit signal_polarity;  // 0 = positive ; 1 = negative
assign signal_corrected = signal ^ signal_polarity;

Now you can use signal_corrected in your assertions. You can certainly call uvm_config_db#(bit)::get() from the interface if it has been set in your testbench. You might need to use uvm_config_db#(bit)::wait_modified() to wait for it to be set before you get it.