iCE40 Ultra Plus 5k — how to set PLL (without propietary GUI tools) (continued)

In this question, I was suggested to use the existing libraries in order to test a PLL for the iCE40 Ultra Plus 5k.

I bought the Icebreaker V1.0e board and it looks like this:

External 12 MHz oscilator is connected to the pin 35 (marked green) of the Lattice iCE40UP5k (package SG48).

Pin 35 has function: IOT_46b_G0, type: DPIO/GBIN0 and is located in bank: 0).

When I searched the library that I posted above, I found a nice primitive SB_PLL40_PAD on the page 98. This primitive's description precisely matches what was done on the Icebreaker V1.0e schematics. Here is the description:

Please observe that it matches with the pin description above! Now, I want to use this in my VHDL so for start I only wrote a VHDL wrapper for this primitive:

-- A:
library ieee;
use ieee.std_logic_1164.all;

-- B:
entity pll_icebreaker is port(
    C1_1: in std_ulogic;
    C1_2: out std_ulogic;
    C1_3: out std_ulogic;
    C1_4: out std_ulogic;
    C1_5: in std_ulogic;
    C1_6: in std_ulogic_vector (6 downto 0);
    C1_7: in std_ulogic;
    C1_8: in std_ulogic;
    C1_9: in std_ulogic
);
end pll_icebreaker;

-- C:
architecture logic_001 of pll_icebreaker is

    -- D:
    component SB_PLL_40_PAD is port (
        PACKAGEPIN: in std_ulogic;
        PLLOUTGLOBAL: out std_ulogic;
        PLLOUTCORE: out std_ulogic;
        LOCK: out std_ulogic;
        EXTFEEDBACK: in std_ulogic;
        DYNAMICDELAY: in std_ulogic_vector (6 downto 0);
        RESETB: in std_ulogic;
        BYPASS: in std_ulogic;
        LATCHINPUTVALUE: in std_ulogic
    );
    end component;

begin

    -- E:
    C1: SB_PLL_40_PAD port map(
        PACKAGEPIN => C1_1,
        PLLOUTGLOBAL => C1_2,
        PLLOUTCORE => C1_3,
        LOCK => C1_4,
        EXTFEEDBACK => C1_5,
        DYNAMICDELAY => C1_6,
        RESETB => C1_7,
        BYPASS => C1_8,
        LATCHINPUTVALUE => C1_9
    );

end architecture logic_001;

Now I try to compile this VHDL design using this makefile target all (only FOSS tools are used):

# A:
file_main = pll_icebreaker
file_pcf = icebreaker

module_top = pll_icebreaker
entity_top = $(module_top)

####################################################################################################

# B:
all:
    yosys \
        -m ghdl \
        -p "ghdl $(file_main).vhdl -e $(entity_top); write_verilog $(file_main).v"
    yosys \
        -p "synth_ice40 -top $(module_top) -blif $(file_main).blif" \
        $(file_main).v
    arachne-pnr \
        -d 5k \
        -P sg48 \
        -o $(file_main).asc \
        -p $(file_pcf).pcf $(file_main).blif
    icepack $(file_main).asc $(file_main).bin

And my toolchain complains that it can not find the module SB_PLL_40_PAD:

2.2.1. Analyzing design hierarchy..
Top module:  \pll_icebreaker
ERROR: Module `\SB_PLL_40_PAD' referenced in module `\pll_icebreaker' in cell `\c1' is not part of the design.
make: *** [makefile:81: all] Error 1

How come? Isn't the Lattice technology library implemented in Yosys tools? I am a bit confused... How can I solve this problem?

It looks like I can't read. Lattice technology library mentions SB_PLL40_PAD:

and I used SB_PLL_40_PAD... So of course it could not work! Now it compiles!

So I have a start here in order to create a nice PLL example that is using pre-existing hardware inside FPGA!