exceptionriscvriscv32

How to clear an exception in handler in risc-v?


Following is my trap routine in FE310 Sifive-Hifive1-Rev B board.

my_trap_routine:

    // read mcause
    csrr t0, mcause;

    // read mepc
    csrr t1, mepc;

mret;

Now, I generated a load access fault exception and execution jumped inside the trap routine. Now how to clear the exception inside the handler so that it don't keep jumping into trap routine again and again?


Solution

  • It is more about how to handle/ignore the exception and where to resume the excepting program, rather than clearing the exception.

    Ideally, you will emulate the ecxepting instruction, so that then the interrupted code is concievably resumable, and then resume the program.

    You have to advance the exception program counter, so that you return to the next instruction after in the user / interrupted code.

    This is fairly simple in RISC V unless the compressed instruction set is in use, in which case you have to decode the excepting instruction to determine how far to advance the PC.

    Fortunately, it is a pretty simple decode, but you need to be aware that RISC V allows varying instruction length in sizes of 2 byte increments.