[SOLVED] Why Yosys synthesis the sequential statement to constant

Why Yosys synthesis the sequential statement to constant

I have the Verilog statement below:

module test (A,B, CLK);
input  A, CLK;
output B;

    always@(posedge CLK) 
        if(A) B <= 1'b1;

endmodule

I am expecting a register. However, after I synthesis it with Yosys, I got the result as follow:

assign B = 1'b1;

I don't understand why Yosys translate the above Verilog statement to a constant 1.

Please advice, thanks!

Solution

Your B has two possible values:

1'b x during initialization (more in IEEE Std 1364 4.2.2 Variable declarations),
1'b 1 when A is equal to 1'b 1.

You really have only one value. Thats mean you can optimize it to hardwired 1'b 1.

This is not a Yosys fault. All (or almost all) synthesis software will behave same way. If you want to let it work (if I guess what you want), you have to allow B to take two different values. You can do it by initial value equal to 1'b 0 or by reset to value 1'b 0.

I suggest to use reset instead of initial value because initial value can be implemented as A connected to register's set pin.