I need to convert this VHDL code to MyVHDL Python, how to?

i need to convert this code to myhdl in python for my school work, anyone can help me?

library ieee;
use ieee.std_logic_1164.all;

entity simple_example is
    port (
        a : in std_logic;
        b : in std_logic;
        o : out std_logic   
    );
end simple_example;

architecture simple_example of simple_example is
    signal s : std_logic;
begin

    s <= a and b;
    o <= s or b;

end simple_example;

You may refer to the docs at: http://docs.myhdl.org/en/stable/manual/preface.html#

You may find the below helpful:

from myhdl import *

@block
def simple_example(a , b, o):
    """
        input: a, b
        output: o
    """
    @always_comb
    def behave():
        s = a and b
        o = s or b
    return instances()


"""
Verification
"""

x = Signal(bool(0))
y = Signal(bool(0))
z = Signal(bool(0))

test = simple_example(x, y, z)
test.convert(hdl="VHDL", initial_values=True)