Yosys -- compilation of .dot file suceeds, but viewer (xdot) can't preview it

I have two modules, each in sepparate verilog file. One file is double_shift_reg.v with the top module double_shift_reg:

`include "./shift_reg.v"

`default_nettype none

module double_shift_reg(clk, shi, in, out);

    input wire clk; // Clock
    input wire shi; // Shift enable
    input wire in; // Input information
    output wire out; // Output information

    wire d1; // Data 1
    wire d2; // Data 2

    shift_reg r1(.clk(clk), .rst(1'b0), .shi(shi), .in(in), .out(d1));
    shift_reg r2(.clk(clk), .rst(1'b0), .shi(shi), .in(in), .out(d2));

    assign out = d1 ^ d2;


    `ifdef FORMAL
        
        reg [2:0] f_counter;
        always @(posedge clk)
        begin
            assert(out == 0);
            f_counter = f_counter + 1;
            if (f_counter == 1'b1111)
                assume(shi);

        end

    `endif // FORMAL  

endmodule

The other file is a shift_reg.v with a module shift_reg that is used inside the top module:

`default_nettype none

module shift_reg(clk, rst, shi, in, out);

    input wire clk; // Input clock
    input wire rst; // Input reset
    input wire shi; // Shift enable
    input wire in; // Input information
    output wire out; // Output bit

    parameter wid = 8; // Shift register's width
    
    parameter ini = {{(wid - 1){1'b0}}, 1'b1}; // Shift register's initial state

    reg [(wid - 1):0] s_reg;
    initial s_reg = ini;

    always @(posedge clk)
    begin
        if(rst)
            s_reg <= ini;
        else if(shi)
            s_reg[(wid - 1):0] <= {in, s_reg[(wid - 1):1]};
    end

    assign out = s_reg[0];

endmodule

Then I try to create and preview a .dot file with:

yosys \
    -p "read_verilog -sv -formal double_shift_reg.v" \
    -p "hierarchy -check -top double_shift_reg" \
    -p "proc" \
    -p "show -prefix $(file_main) -notitle -colors 2 -width -format dot"
xdot $(file_main).dot

Compilation messages for the last part i.e. -p "show -prefix $(file_main) -notitle -colors 2 -width -format dot" looks like this:

-- Running command `show -prefix double_shift_reg -notitle -colors 2 -width -format dot' --

4. Generating Graphviz representation of design.
Writing dot description to `double_shift_reg.dot'.
Dumping module double_shift_reg to page 1.
Dumping module shift_reg to page 2.

Warnings: 1 unique messages, 1 total
End of script. Logfile hash: e53dd145db
CPU: user 0.02s system 0.01s, 

There is just one warning, no errors... But when I .dot is opened by previewer, I get an error:

This never happened when I was creating .dot files for only a single verilog file with a single module inside. Am I missing some crutial part?

I found a solution! I was missing one line that adds the library. This makefile target works:

dot:
    yosys \
        -p "read_verilog -sv -formal $(file_main).v" \
        -p "read_verilog -lib +/ice40/cells_sim.v" \
        -p "hierarchy -check -top $(module_top)" \
        -p "proc" \
        -p "show -prefix $(file_main) -notitle -colors 2 -width -format dot"
    xdot $(file_main).dot