verilogclockdigitaledaplayground

Why does this Verilog module show "invalid module item" on the 9th line?

I was learning about loops in Verilog and wanted to create a simple clock with time period of 20ns. I am getting the error below whenever I am trying to run the code in EDA Playground.

module Pulse(clock);
  output reg clock;
  
  initial
    begin
      clock = 1'b0;
    end
  
  forever #10 clock = ~clock;      //Error is here
endmodule

design.sv:9: syntax error design.sv:9: error: invalid module item.

Solution

  • forever cannot be used outside of a procedural block. It will work if you put it the initial block:

    initial
   begin
      clock = 1'b0;
      forever #10 clock = ~clock;  
   end