hardwarehdlnand2tetris

Encounter [0]: sub bus of an internal node may not be used when implementing Not16 with Not

When I was implementing Not16 with Not gates:

CHIP Not16 {
    IN in[16];
    OUT out[16];
  
    PARTS:
        Not(in=[0], out=out[0]);
        Not(in=[1], out=out[1]);
        Not(in=[2], out=out[2]);
        Not(in=[3], out=out[3]);
        // ...
        Not(in=[15], out=out[15]);

I got an error "[0]: sub bus of an internal node may not be used" on the first part.

However, implementing this with 16 Nand gates is fine:

Nand(a=in[0], b=in[0], out=out[0]);
// ...

Can someone please point to the issue and difference.

p.s. Using HardwareSimulator from Nand2Tetris

Solution

  • I believe you have typos in your Not components. The in should be in the form in=in[x], not in=[x] as you have it currently.

    Conversely, your Nand components are properly formatted.