I'm working on a program that will take a value in BCD, convert it to binary, and count down for the given value to 0. The BCD conversion module works perfectly, but it seems my 'microwave' module is not being called.
My output of this program is:
time = xxxxxxxx bcdtime = 0001 0010
time = 00001100 bcdtime = 0001 0010
I can see the conversion, but the countdown does not occur. Can anyone explain where I might be going wrong or point me in the direction of resources that could help me answer this? My code is below:
module bcd_to_bin(bintime,bcdtime1,bcdtime0);
input [3:0] bcdtime1,bcdtime0;
output [7:0] bintime;
assign bintime = (bcdtime1 * 4'b1010) + {3'b0, bcdtime0};
endmodule
module microwave(bintimeout, Clk, Start, Stop, bintime, status);
input [7:0] bintime;
input Clk, Start, Stop;
output reg [7:0] bintimeout;
output reg status;
always @ (posedge Start)
begin
assign bintimeout = bintime;
end
always @ (posedge Clk)
begin
bintimeout = bintimeout - 1;
end
endmodule
module t_microwave;
wire status;
wire [7:0] bintimeout;
reg Clk=1; reg Start, Stop;
reg [3:0] bcdtime1, bcdtime0;
wire [7:0] bintime;
microwave M2 (bintimeout, Clk, Start, Stop, bintime, status);
bcd_to_bin M3 (bintime,bcdtime1,bcdtime0);
always #10 Clk = ~Clk;
initial
begin
Start = 0; Stop = 0; bcdtime1 = 4'b0001; bcdtime0 = 4'b0010;
#10 Start = 1; #10 Start = 0;
end
initial #10000 $finish;
initial
begin
$monitor ("time = %b, bcdtime = %b %b ", bintimeout, bcdtime1, bcdtime0);
end
endmodule
There are a few issues with your code.
If you want to guarantee that your design captures the Start
pulse, you should make sure it is high for one clock period (20). Change:
#10 Start = 1; #10 Start = 0;
to:
#10 Start = 1; #20 Start = 0;
In the microwave
module, you should assign to bintimeout
in one always
block, not two, and there is no need to use the assign
keyword inside an always
block. Also, good coding practices recommend using nonblocking assignments (<=
) for sequential logic. This is a better way to code the module:
module microwave(bintimeout, Clk, Start, Stop, bintime, status);
input [7:0] bintime;
input Clk, Start, Stop;
output reg [7:0] bintimeout;
output reg status;
always @ (posedge Clk) begin
if (Start) begin
bintimeout <= bintime;
end else begin
bintimeout <= bintimeout - 1;
end
end
endmodule
This is the output now, which shows the count-down:
time = xxxxxxxx, bcdtime = 0001 0010
time = 00001100, bcdtime = 0001 0010
time = 00001011, bcdtime = 0001 0010
time = 00001010, bcdtime = 0001 0010
time = 00001001, bcdtime = 0001 0010
time = 00001000, bcdtime = 0001 0010
time = 00000111, bcdtime = 0001 0010
time = 00000110, bcdtime = 0001 0010
time = 00000101, bcdtime = 0001 0010
time = 00000100, bcdtime = 0001 0010
time = 00000011, bcdtime = 0001 0010
time = 00000010, bcdtime = 0001 0010
time = 00000001, bcdtime = 0001 0010
time = 00000000, bcdtime = 0001 0010
time = 11111111, bcdtime = 0001 0010
time = 11111110, bcdtime = 0001 0010