How to fix [Common 17-1293] error in Xilinx Vivado?

I was trying to run some simple behavioral simulations in Xilinx Vivado, but then I got the error -

[Common 17-1293] The path 'D:/Deepan/Text Books/internship/test/test.cache/wt' already exists, is a directory, but is not writable.

The Verilog files that I wanted to run used to work perfectly before, but suddenly it broke.

I made sure that the directory has proper access and was not stuck at read-only, still, I kept getting the error.

I kept getting the same error for both v2021.1 and v2020.3.

The files I wanted to run -

`timescale 1ns / 1ps

module Mealy_Sequence(
        input wire clk,
        input wire reset,
        input wire level,
        output reg tick
    );
    
    localparam  //The Mealy states
        zero = 1'b0,
        one = 1'b1;
    
    reg current_state, next_state;
    
    always  @(posedge clk, posedge reset)
    begin
        if(reset)
            current_state <= zero;
        else
            current_state <= next_state;
    end
    
    always  @(current_state, level)
    begin
        case(current_state)
            zero:   begin
                    if(level)
                        begin
                            next_state <= one;
                            tick <= 1;
                        end
                    else
                        begin
                            next_state <= current_state;
                            tick <= 0;
                        end
                    end
            one:    begin
                    if(level)
                        begin
                            next_state <= one;
                            tick <= 0;
                        end
                    else
                        begin
                            next_state <= zero;
                            tick <= 0;
                        end
                    end
        endcase
    end
    
endmodule

test bench -

`timescale 1ns / 1ps

module Sequence_Test_Mealy;

    reg clk;
    reg reset;
    reg level;
    wire tick;

    Mealy_Sequence x(
        .clk(clk),
        .reset(reset),
        .level(level),
        .tick(tick)
    );

    always #5 clk = ~clk;
    always #15 level = ~level;

    initial
    begin
        clk <= 0;
        level <= 0;
        reset <= 1;
        #10 reset <=0;
    end

endmodule

Even though I had no spaces in the path names but I was still getting this error.

I solved this by making the path extremely small e.g., D:/a/a/a.xpr