cembeddedmicrocontrollermsp430

MSP430 ADC, using a different memory slot other than MEM0


I'm working with the MSP430Ware Sample Code for a basic ADC on the MSP-EXP430FR5994 development board. On the code, it uses MEM0 and the supporting infrastructure such as flag 0 to convert. The one underneath is my modification; I've used MEM2 and flag 2 to convert.

#include <msp430.h>
#include <stdio.h>

int main(void)
{
WDTCTL = WDTPW | WDTHOLD;               // Stop WDT

// GPIO Setup
P1OUT &= ~BIT0;                         // Clear LED to start
P1DIR |= BIT0;                          // Set P1.0/LED to output
P1SEL1 |= BIT2;                         // Configure P1.2 for ADC input (See p369, p88 of specific for pin config details.)
P1SEL0 |= BIT2;                         // There are two Pin Select bits (p88 of specifics, we are given that P1.2 corresponds to A2.)

// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings (p92)
PM5CTL0 &= ~LOCKLPM5;

// Configure ADC12
ADC12CTL0 = ADC12SHT0_2 | ADC12ON;      // Sampling time, S&H=16, ADC12 on [p893, CTL0 = control 0, SHT0_2 = sample & hold time, knowledge of register value from p88_s]
ADC12CTL1 = ADC12SHP;                   // Use sampling timer [p895, Sampler uses sampling timer (not sure what that is yet)]
ADC12CTL2 |= ADC12RES_2;                // 12-bit conversion results [p897, RES means resolution, _2 means 12 bits]
ADC12CTL3 |= ADC12CSTARTADD_3;          // Use MEM3/MCTL3
//ADC12MCTL0 |= ADC12INCH_2;
ADC12MCTL3 |= ADC12INCH_2;              // A2 ADC input select; Vref=AVCC [MCTL2 = Memory Control 2 (p900), INCH = input channel, 2 means channel A2]
ADC12IER0 |= ADC12IE3;                  // Enable ADC conv complete interrupt [p903, means "interrupt enable register 0". Enables or disables the interrupt request for ADC12IFG2 bit]
printf("Got here.\n");

while (1)
{
    printf("Got there.\n");
    __delay_cycles(5000);
    ADC12CTL0 |= ADC12ENC | ADC12SC;    // Start sampling/conversion [p893, ENC = enable conversion, SC = start conversion. difference between the two = idfk, but remember to have both set]

    __bis_SR_register(LPM0_bits | GIE); // LPM0, ADC12_ISR will force exit

   // printf("Got nowhere.\n");
    __no_operation();                   // For debugger
}
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = ADC12_B_VECTOR
__interrupt void ADC12_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_B_VECTOR))) ADC12_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(ADC12IV, ADC12IV__ADC12RDYIFG))
{
    case ADC12IV__NONE:        break;   // Vector  0:  No interrupt
    case ADC12IV__ADC12OVIFG:  break;   // Vector  2:  ADC12MEMx Overflow
    case ADC12IV__ADC12TOVIFG: break;   // Vector  4:  Conversion time overflow
    case ADC12IV__ADC12HIIFG:  break;   // Vector  6:  ADC12BHI
    case ADC12IV__ADC12LOIFG:  break;   // Vector  8:  ADC12BLO
    case ADC12IV__ADC12INIFG:  break;   // Vector 10:  ADC12BIN
    case ADC12IV__ADC12IFG0:            // Vector 12:  ADC12MEM0 Interrupt
        if (ADC12MEM0 >= 0x7ff){           // ADC12MEM0 = A1 > 0.5AVcc?
            P1OUT |= BIT0;              // P1.0 = 1
        }
        else{
            P1OUT &= ~BIT0;             // P1.0 = 0
        }
        printf("In MEM0.");
        ///int memval = ADC12MEM0;             // Memory stored in MEM0, because it was set from above.
        ///printf("%d\n", memval);
            // Exit from LPM0 and continue executing main
            __bic_SR_register_on_exit(LPM0_bits);
        break;
    case ADC12IV__ADC12IFG1:   break;   // Vector 14:  ADC12MEM1
    case ADC12IV__ADC12IFG2:   break;   // Vector 16:  ADC12MEM2
        if (ADC12MEM2 >= 0x7ff) {        // ADC12MEM2 = A1 > 0.5AVcc?
            P1OUT |= BIT0;  }            // P1.0 = 1
        else{
            P1OUT &= ~BIT0;  }           // P1.0 = 0
        printf("In MEM2.");
        int memval = ADC12MEM2;             // Memory stored in MEM0, because it was set from above.
        printf("%d\n", memval);
            // Exit from LPM0 and continue executing main
            __bic_SR_register_on_exit(LPM0_bits);
            break;
    case ADC12IV__ADC12IFG3:   break;   // Vector 18:  ADC12MEM3
    case ADC12IV__ADC12IFG4:   break;   // Vector 20:  ADC12MEM4
    case ADC12IV__ADC12IFG5:   break;   // Vector 22:  ADC12MEM5
    case ADC12IV__ADC12IFG6:   break;   // Vector 24:  ADC12MEM6
    case ADC12IV__ADC12IFG7:   break;   // Vector 26:  ADC12MEM7
    case ADC12IV__ADC12IFG8:   break;   // Vector 28:  ADC12MEM8
    case ADC12IV__ADC12IFG9:   break;   // Vector 30:  ADC12MEM9
    case ADC12IV__ADC12IFG10:  break;   // Vector 32:  ADC12MEM10
    case ADC12IV__ADC12IFG11:  break;   // Vector 34:  ADC12MEM11
    case ADC12IV__ADC12IFG12:  break;   // Vector 36:  ADC12MEM12
    case ADC12IV__ADC12IFG13:  break;   // Vector 38:  ADC12MEM13
    case ADC12IV__ADC12IFG14:  break;   // Vector 40:  ADC12MEM14
    case ADC12IV__ADC12IFG15:  break;   // Vector 42:  ADC12MEM15
    case ADC12IV__ADC12IFG16:  break;   // Vector 44:  ADC12MEM16
    case ADC12IV__ADC12IFG17:  break;   // Vector 46:  ADC12MEM17
    case ADC12IV__ADC12IFG18:  break;   // Vector 48:  ADC12MEM18
    case ADC12IV__ADC12IFG19:  break;   // Vector 50:  ADC12MEM19
    case ADC12IV__ADC12IFG20:  break;   // Vector 52:  ADC12MEM20
    case ADC12IV__ADC12IFG21:  break;   // Vector 54:  ADC12MEM21
    case ADC12IV__ADC12IFG22:  break;   // Vector 56:  ADC12MEM22
    case ADC12IV__ADC12IFG23:  break;   // Vector 58:  ADC12MEM23
    case ADC12IV__ADC12IFG24:  break;   // Vector 60:  ADC12MEM24
    case ADC12IV__ADC12IFG25:  break;   // Vector 62:  ADC12MEM25
    case ADC12IV__ADC12IFG26:  break;   // Vector 64:  ADC12MEM26
    case ADC12IV__ADC12IFG27:  break;   // Vector 66:  ADC12MEM27
    case ADC12IV__ADC12IFG28:  break;   // Vector 68:  ADC12MEM28
    case ADC12IV__ADC12IFG29:  break;   // Vector 70:  ADC12MEM29
    case ADC12IV__ADC12IFG30:  break;   // Vector 72:  ADC12MEM30
    case ADC12IV__ADC12IFG31:  break;   // Vector 74:  ADC12MEM31
    case ADC12IV__ADC12RDYIFG: break;   // Vector 76:  ADC12RDY
    default: break;
}
}

Testing via the terminal suggests it gets to "Got there" and then bricks itself. I am also receiving a warning on line "if (ADC12MEM2 >= 0x7ff)" stating that the code does not reach it, which is bad because that's the interrupt I need to get to (at least, that's what I think).

If any more details are needed to resolve this issue please let me know.


Solution

  • The issue has been resolved.

    case ADC12IV__ADC12IFG2:   break;   // Vector 16:  ADC12MEM2
        if (ADC12MEM2 >= 0x7ff) {        // ADC12MEM2 = A1 > 0.5AVcc?
        ...
        break;
    

    There was a break before the interrupt flag's content, which meant the interrupt would not reach the content. The correct code is now:

    case ADC12IV__ADC12IFG2:     // Vector 16:  ADC12MEM2
        if (ADC12MEM2 >= 0x7ff) {        // ADC12MEM2 = A1 > 0.5AVcc?
        ...
        break;