What are ps and delta values in Modelsim Verilog?
I am new to Modelsim. I have a processor. In this module clock cycle is 40 ps and I simulate the project with 20 ps speed.
forever #20 clk=~clk;
I have added some variables to the list to be able to see their values in each cycle. But I've realized that there are ps and delta values that occur after one clock cycle.
This is created after 80 ps.
This is created 40 ps later.(One clock cycle)
See there are +1 +2 +3 +4. I assume they are related to some time value but couldn't understand exactly. I know that in each @nedege (towards 0,from 1 to 0) pc is loaded. My question is why do I see different number of clock cycle times.(For 0 there are 5 rows, for 20 there is only one,for 40 there 2 and so on)
Why are their occurrances in the list view different? Because from my perspective when clock is changed from 1 to 0 current instruction is loaded. But in the image as you can see -in 40ps rows- current instruction is different. The one with +1 is current instruction but the one with +2 is next instruction.
And what is the meaning of these delta values? As far as I know, there are 3 different timing control in Modelsim(delay-based timing control,event-based timing control,level-sensetive timing control). I guess I am using delay-based timing control by using @posedge and @nededge keywords.
In Verilog simulators time evolves from event to event, so they are called event-driver simulators.
Actually execution evolves through a number of region where events are scheduled to advance simulation. What you are seeing is the evolution from one delta-delay to another in the same cycle.
At 20ps, probably it's happening the clock negedge and no events are scheduled further.
At 40ps, probably it's happening the posedge of clock. This event has effect on all signals that are waiting for @posedge and that have to be updated. So the scheduler adds some events to the event-queue, one each signal, and after minimum time advance (+ 1 delta delay), the simulator evaluates the highest priority one.
Delta-delay is the minimum timeunit advance possible. If you print all signals in your design, you can check which one is updated at each event.
Remember that evolution inside same cycle could be not deterministic.
More info can be found here: https://electronics.stackexchange.com/q/99223
- Binary - BCD convertor works in sim, but does not work on FPGA
- Does the SystemVerilog standard allows mixing with Verilog files?
- How to concatenate number (1'b1) and `define in a single statement
- Why am I not getting output after pass through design in testbench module driver and monitor?
- Implicit net-type declaration and `default_nettype
- Is there a way to condition on a type?
- Error (10170): HDL syntax errors in Quartus (HDL)
- Error opening .vcd file. No such file or directory
- Ternary operation not working with unary operation
- Unexpected results in fixed-point conversion in Verilog
- Trying to change Hexadecimal display to Signed Decimal in VCD
- How to reuse the genvar in Verilog?
- How to define a module with a parameter in Verilog?
- Generate custom waveform in verilog
- Accessing Verilog genvar generated instances in simulation code
- Extend a value with ones in SystemVerilog
- reg qb; cannot be driven by primitives or continuous assignment
- "Invalid Module Instantiation" Error in Mealy sequence detector - Verilog
- Shift Register Design using Structural Verilog outputs X
- How to write a shift register in a recursive way
- Shift Registers Verilog
- Serial output shift register indetermination
- ShiftRegister Verilog HDL Output giving xxxxxxx
- Declaring variables in Verilog for loop
- Use of inout in task using fork-join_none
- How to initialize the queue of queue?
- Testing multiple configurations of parameterizable modules in a Verilog testbench
- Function to convert logic vector into string
- A function that transforms an integer into a string so that it fits in a designated number of positions and then outputs it
- Can't see anything when accessing RAM contents in simulation