I'm looking into the capabilities of fragment/packet reassembly hardware and wondering whether one could use them to perform application-level packet reassembly.
I have to receive and reassemble a sequence of 65kiB packets (hundreds of streams adding up to 200 or 400Gbit/s) that I need to reorder and assemble (amounting e.g. to large 512kiB frames) in my application before delivering them further to other computation.
Would any existing receive offload hardware be able to help here? Instead of 'just' reassembling on ip+tcp would I be able to tell it to reassemble on ip+udp+ my application level fragment/segment protocol?
Apart from using a custom FPGA, I mean.
edit: I'm working on a Mellanox Connect-x 6 dx NIC, dpdk 21.11, fw 22.32.1010
There are multiple NICs under Mellanox connectx-6, but most of them are classified as SMART NIC. Some of them are referenced under 100Gbps and 200Gbp single and multiple-port PCIe Gen 4 as 1, 2, 3 and 4.
But all the NICs support certain fixed functionality, but not HW IP packet reassembly with connectx-6. With DPDK 22.03 there are options for RTE_ETH_DEV_REASSEMBLY_F_IPV4 |RTE_ETH_DEV_REASSEMBLY_F_IPV46 which is supported on Marvell OCTEON CN9K/CN10K SoC.
An alternative way is to make use of custom FPGA, DPU-2 Bluefield from Mellanox, Intel NetSec one can new create logic like ipv4|ipv6 reassembly.