Number of dsp slices needed for an N-tap FIR filter

I want to determine the total area in terms of dsp slices required to implement an N-tap Direct Form 1 FIR filter with pipelining using the 7 Series DSP48E1 slice. The delays are implemented as flip flops.

What are the equations for calculating the number of slices for the delays, multipliers, adders and pipelines. The filter to be considered is shown in the image.

The input word length is 15 bits and the coefficients are 14 bits. Two pipeline delays are used.

Please assist. Thank you.

Xilinx DSPs can accept inputs up to 18 bits (ref). Given N the number of taps for your FIR, the general formula is that you will need, for each output, N multiplications and N-1 sums.

in order to implement the topology you have pictured here you will need:

• N Flip Flops [14:0] for the delay chain.
• N DSP
• ceil(log2(N)) ADDERS (for the adder tree).

An advice however, is to use the built-in accumulator to implement the additions. Since it is pipelined, you will accumulate the result at each step and pass it to the next multiplier. You will have to take into account the delays, but the general idea is the following:

That can be mapped pretty easily to the Xilinx DSP primitive and does not require external logic.