Will 'typedef logic' generate a register when using it instead of a 'wire', in SystemVerilog?

Having the following SystemVerilog code:

module my_module(
  input  wire [31:0] my_net
);
  ...
endmodule
...
...
wire [31:0] my_net;

assign my_net = ...;

my_module m(my_net);

What are the consequences (at synthesis time) of change the my_net declaration by:

typedef logic [31:0] my_net_t; // This is actually no longer a net, but a variable.

module my_module(
  input  my_net_t my_net
);
  ...
endmodule

my_module m(my_net);
...
...
wire [31:0] my_net;

assign my_net = ...;

my_module m(my_net);

I mean, logic is a variable, not a net, therefore, will the synthesizer generate a register for my_net?

Incorrect. logic is a data type that can be applied to a variable or net.

input  wire [31:0] my_net
input  my_net_t my_net

are implicitly the same as

input  wire logic [31:0] my_net
input  wire my_net_t my_net

When internal to a module

logic v;
wire w;

are implicitly

var logic v;
wire logic W;

But regardless of my_net being a variable or net, a continuous assignment to my_net does not create a register.