Verilog [dot] meaning?

What does this " .depth_log2(7) " and .i_wclk mean in Verilog code?

  asynch_fifo #(.depth_log2(7),
  .data_width(22),
  .rd_flop1_megedge(1'b1),
  ) USB2_ASYNCH_FIFO (
  .i_wclk(i_usb2_sieclockin_ip),
   );

I'm not able to understand what that .depth_log2 and .rd_flop1_megedge means

When you instantiate a module, such module might have some parameters. You can leave them at default, or you can initialize them at the values you prefer. In your example you are setting the depth at 7, the data width at 22 etc..

In general, if you have a verilog module like this:

module my_module
  #(    parameter P1 = 2,
        parameter P2 = 0)

  ( input               clk,
    output  reg [P1-1:0] out);
    
    // Module logic

endmodule

You can instantiate it with the dot notation

    wire         wire_clk;
    wire [2-1:0] wire_out;

    my_module #(.P1(2), 
                .P2(3) ) u0
               ( .clk(wire_clk),
                 .out(wire_out);