Microprocessor data bus and address bus width on a modern x86 CPU?

Hello I am having trouble with the work of finding the width of data bus and address bus as I have seen no tutorials show how to find out that information. I hope that someone can help me as my chip is Intel Core i7-6820HQ 2.7GHz. Here are some information about my chip.

Supported virtual and physical address widths can be queried with CPUID. How to get physical and virtual address bits with C/C++ by CPUID command

Related: Why in x86-64 the virtual address are 4 bits shorter than physical (48 bits vs. 52 long)? 52-bit is the theoretical max physical width an x86-64 CPU could support with the current page-table format. Even the highest of high-end Xeon and Epyc CPUs aren't quite there yet.

As for data bus widths, there are various internal busses between levels of cache, e.g. https://electronics.stackexchange.com/questions/329789/how-can-cache-be-that-fast/329955#329955 shows a Sandybridge. https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Block_Diagram shows your Skylake, with bus widths inside the core, and the 32-byte ring bus.

These aren't things you can query from the CPU at run-time, you just have to look them up from information the vendor as released about that generation of CPU. (e.g. a chip conferences, in promotional material about all the ways their chips are better than ever, and in Intel's optimization manual: https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)

The external memory bus is dual channel DDR4, therefore 64 bits wide on each channel. (With separate address/command signal lines so it can pipeline commands.) https://en.wikipedia.org/wiki/DDR4_SDRAM#JEDEC_standard_DDR4_module . See also How much of ‘What Every Programmer Should Know About Memory’ is still valid? - the basic layout of DDR4 SDRAM is still the same as SDRAM, just higher clocks and some refinements in the commands, so the low-level details about DRAM in Ulrich Drepper's article about memory still apply. (e.g. sending addresses split into row/column, so changing row within the same DRAM "page" is faster.)