verilogsystem-verilogboolean-logicverificationamba

Byte Masking AxiStream: How to mask tdata with tkeep systemverilog

In AxiStream the tkeep value in each transfer denotes the valid bytes in the tdata field of the same transfer. In systemverilog i want to use tkeep to mask (set to 0) the invalid bits in the tdata field.

If tkeep denoted invalid bits then I could simply do:

masked_tdata = tdata & tkeep;

However tkeep denotes valid bytes.

Is there an elegant way to perform this "Byte Masking" operation in SystemVerilog (Does not have to be synthesizable as this is part of a testbench).

logic[31:0] tdata = 4'hC1FF
logic[3:0] tkeep = 4'b0001;
logic[31:0] masked_tdata;


assign masked_tdata = tdata & tkeep; // evaluates to 0x0001
// what I want it to evaluate to is 0x000F
Solution

  • If by elegant you mean as a single expression, I can't think of one that is more elegant than using for loop.

    for(int i;i<$bits(tdata)/8;i++)
  masked_tdata[i*8+:8] = tkeep[i] ? tdata[i*8+:8] : '0;