Elaboration task '$dumpvars' requires SystemVerilog
is the error that is showing in the terminal when I execute
iverilog -o test_tb.vvp test_tb.v
Similar for $dumpvars.
The codes are:
//design
module test (a,b);
input a;
output b;
assign b=a;
endmodule
//testbench
`timescale 1ns/1ns
`include "test.v"
module test_tb ();
reg a;
wire b;
test uut(a,b);
$dumpfile("test_tb.vcd");
$dumpvars(0,test_tb);
initial begin
a=0;
#20;
a=1;
#20;
a=0;
#20;
$display("test complete");
end
endmodule
The system task calls need to be in an initial block like this:
initial begin
$dumpfile("test_tb.vcd");
$dumpvars(0,test_tb);
end