I study to work with FPGA (Xilinx Kintex Ultrascale). In Vivado i create blockdesign with my module (gen_data) and Microblaze (soft processor for XILINX fpga). Connect with Microblaze across AXI_GPIO (have 1 input and Interrupt Enable). Gen_data is simple module (source code). Frequency is 100 Mhz.
entity generate_data is
port (
clk : in std_logic;
out_data : out std_logic
);
end generate_data;
architecture Behavioral of generate_data is
begin
process (clk)
variable counter : integer := 0;
begin
if rising_edge(clk) then
counter := counter + 1;
if counter = 100000 then
out_data <= '1';
counter := 0;
end if;
end if;
end process;
end Behavioral;
On Microblaze side i set interrupt but it is doesnt work.
What i need to do for work interrupt with module gen_data? Thanks.
But if i change my module (gen data) on some button then interrupt will work good. For AXI_GPIO button is 1 input bit (similar to gen_data).
You never set data_out to '0' so once it goes to 1, it stays there forever. The following drives data_out to '0' and moves "count := count + 1" so that the check, counter = 100000, is against the register output rather than the newly incremented value.
entity generate_data is
port (
clk : in std_logic;
out_data : out std_logic
);
end generate_data;
architecture Behavioral of generate_data is
begin
process (clk)
variable counter : integer := 0;
begin
if rising_edge(clk) then
if counter = 100000 then
out_data <= '1';
counter := 0;
else
out_data <= '0';
counter := counter + 1
end if;
end if;
end process;
end Behavioral;