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How to use XADC's GPIO on Xilinx KC705 FPGA

I output the clock generated through GPIO, but I cannot check the data on the oscilloscope.

I am developing using the AMD Kintex7 FPGA KC705 Evaluation Kit and using the Vivado 2022.2 version.

I want to use the GPIO of XADC and output the created clock to GPIO_0 using the port below. enter image description here

I found some information about the pins (XDC files) provided by Xilinx and used them.

set_property PACKAGE_PIN AA27 [get_ports XADC_GPIO_3] 
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_3] 
set_property PACKAGE_PIN AB28 [get_ports XADC_GPIO_2] 
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2] 
set_property PACKAGE_PIN AA25 [get_ports XADC_GPIO_1] 
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1] 
set_property PACKAGE_PIN AB25 [get_ports XADC_GPIO_0] 
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0]

This is the code I used for testing. The generation of clock data was confirmed through the LED and annotated as an error related to LVMOS.

.v

`timescale 1ns / 1ps

module top(
    input rst,
    input clk_p,
    input clk_n,
    //output [7:0] leds,
    output gpio_0
);

wire            clk;

IBUFDS #(
    .DIFF_TERM("FALSE"),
    .IBUF_LOW_PWR("TRUE"),      
    .IOSTANDARD("DEFAULT")      
) IBUFDS_inst (
    .O(clk),                    
    .I(clk_p),              
    .IB(clk_n)                  
);

reg     [31:0]  counter;
always @ (posedge clk or posedge rst)
    if(rst)
        counter <= 0;
    else
        counter <= counter + 1'b1;

//assign            leds = counter[31:24];
assign          gpio_0 = counter[10];
endmodule

.xdc

set_property PACKAGE_PIN AD12 [get_ports clk_p]
set_property IOSTANDARD LVDS [get_ports clk_p]
set_property IOSTANDARD LVCMOS15 [get_ports rst]
set_property PACKAGE_PIN G12 [get_ports rst]
#set_property PACKAGE_PIN AB8 [get_ports {leds[0]}]
#set_property PACKAGE_PIN AA8 [get_ports {leds[1]}]
#set_property PACKAGE_PIN AC9 [get_ports {leds[2]}]
#set_property PACKAGE_PIN AB9 [get_ports {leds[3]}]
#set_property PACKAGE_PIN AE26 [get_ports {leds[4]}]
#set_property PACKAGE_PIN G19 [get_ports {leds[5]}]
#set_property PACKAGE_PIN E18 [get_ports {leds[6]}]
#set_property PACKAGE_PIN F16 [get_ports {leds[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[6]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[5]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[4]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[0]}]
set_property PACKAGE_PIN AB25 [get_ports gpio_0]
set_property IOSTANDARD LVCMOS33 [get_ports gpio_0]

I would like to know how to use XADC's GPIO or if it is possible to use that port.

AMD Kintex7 FPGA KC705 Evaluation Kit

Solution

  • The XADC of the FPGA KC705 is used for temperature and debugging of the FPGA, and the GPIO is also used to receive input.

    To implement the system, you must use the FMC of KC705.

    enter image description here