How to concatenate strings in Icarus Verilog?

I have a SV printing task that concatenates some input strings and prints a message. This code works on Cadence's tools, but when I tried porting to iverilog, I get compile errors.

    task Error (
        input string msg,
        input string name = ""
    );
        begin
            $timeformat(-9, 2, " ns", 12);
            name = (name.len() > 0) ? {_ModuleName(name), ": "} : "";
            $display("  Error: at %0t: %0s%0s", $time, name, msg);
        end
    endtask

And the error message: error: Data types string and bool of ternary do not match.

I guess this may be unsupported by tools, but I could not find an exact reference on this. I suspect strings concatenation may not work as I expect, but again - hard to find info on concatenation supported by iverilog.

# iverilog -v
Icarus Verilog version 12.0 (stable) (s20221226-238-g9e4c4d546)

Your syntax is legal for IEEE Std 1800 (SystemVerilog). Many simulators support the syntax, but your version of iverilog does not (and neither does the version I have). If your version is new, then this syntax is just not supported yet.

You can use an if/else instead of a ternary operator. Obviously, this code is more verbose, but it works if you are stuck with iverilog:

module tb;
task Error (
        input string msg,
        input string name = ""
    );
        begin
            $timeformat(-9, 2, " ns", 12);
            if (name.len() > 0) begin
                $display("  Error: at %0t: %0s:%0s", $time, name, msg);
            end else begin
                $display("  Error: at %0t: %0s", $time, msg);
            end
        end
endtask

initial begin
    #3 Error("aaa", "bbb");
    #3 Error("ccc");
end
endmodule

I have not found a list of SystemVerilog features supported by iverilog. You find out what's supported mostly by trial and error. Before I wrote the code above, I tried constructing a string using $sformatf, but the iverilog version I have gave me an error.