What goes under the hood when a x86 processor accesses memory

I'm going through different material to understand what's the behavior when a x86 instruction access memory (implicitly or explicitly). So far, I believe this is the step-by-step process:

• Effective address is calculated based on the DS,
• If page containing the address is not present:
  • The TLB is checked for the page containing the address to be accessed,
    • If not present in the TLB: the MMU translates the virtual address to a physical address
    • add the new translation to the TLB
  • Load the page
• Access the page

Is this correct? What am I missing?

• Determine the effective address (i.e., offset).
• Calculate the linear address based on the segment.
• Simultaneously,
  • Check the L1 cache for the line containing the address.
  • Check the TLB for the page containing the address.
  • If both of the above hit and the memory type and access type are cachable, perform the access to the cache. (I'm not going to go into the other memory types.)
• If not present in the TLB (or insufficient permissions),
  • Perform a page walk to translate the virtual address to a physical address.
  • If the page walk fails, raise a page fault.
  • If the page walk succeeds, add the translation to the TLB.
• If the memory type and access type are cachable, acquire the cache line and perform the access to the cache.