I am writing a simple Verilog module, that needs to have restrictions on its parameter values. By that I mean only certain values are allowed to be assigned to a generic parameter. I know this could be done in VHDL, is there an equivalent or a workaround in Verilog? I am asking this question because the Xilinx compiler seems to see a corner case value that would never occur if my parameter was in a range.
I have tried checking my parameter in an initial block and doing a $fatal if it is out of the permitted range. That seems to be a very dirty solution...
If you can use SystemVerilog, which Vivado supports, this is easy using a generate-if block.
module top;
dut #(1) u1 ();
endmodule
module dut;
parameter p;
if (!( p inside {[2:3]}) ) $fatal("sorry");
endmodule