What's the difference between dispatching and issuing in CPU pipeline

In Software Optimization Guide for the AMD Zen4 Microarchitecture, the terminology are explained as follows:

• Dispatching: Dispatching refers to the act of transferring macro ops from the front end of the processor to the out-of-order backend.
• Issuing: Issuing refers to the act of picking from the scheduler to send a micro op into an execution pipeline. Some macro ops may be issued as multiple micro ops into different execution pipelines.

It seems that the Dispatch stage is before the Issue stage, which differs from this diagram.

However, according to the content in this article, the dispatch should follow closely the decode stage, which agree with the AMD Terminology.

I tend to think that the process should be:

1. the instruction is decoded into macro-ops at the front end
2. macro-ops are dispatched into the ROB (re-order buffer)
3. after the execution unit/data dependency is ready, macro-ops are decomposed into micro-ops and issued into the execution unit.

For AMD EPYC series CPUs:

• Am I right?

• When we say port in CPU micro-architecture, does it correspond to the issuing or the dispatching?

For Intel Xeon series CPUs:

• Does Intel use the same terminology?

Intel uses opposite terminology from most of the rest of the computer architecture world.

In Intel terminology for out-of-order exec CPUs:

• Issue is when uops are sent from the front-end into the back-end (scheduler and reorder buffer (ROB)), happening along with renaming their registers and allocating them to an execution port
• Dispatch is sending a uop to an execution port (from the scheduler aka reservation station).

For most computer-architecture textbooks, papers, and discussion of non-x86 CPUs, the two terms are simply swapped.

It seems AMD doesn't use Intel's terminology either, so it's an Intel thing, not an x86 thing.