Difference between combinatoric signal dependant on clocked signal vs. registering it

I'm currently writing some VHDL code for a FPGA where a done signal is set through a state machine. The fsm feeds data into a shiftregister and asserts 'done' when it's complete.

Now there are two methods of driving this done signal:

The first way would be to write its next signal one clock cycle beforehand so it changes to '1' when the the last bit is read in. The other way would be to drive it combinatorically such that is is set during the last bit shifting in.

I know that it registering it will hold done high when it transitions back to the start/idle state and not for the combinatoric way, this is not of interest to me.

What I'd like to know is, what would be the preferred way, is there any meaningful difference and do I run into some sort of trouble going one way or the other?

I can see that the combinatoric way would take longer for the signal to resolve since done will only start resolving once the state machine is in the last state which would add additional delay of a MUX probably.

Pros of combinational output:

• No extra 1-cycle latency caused by output registers.
• No extra cell area from output registers.

Pros of registered output:

• No glitches or transient states on output signals.
• The timing paths are less complicated. Which means the design can achieve higher clock speed.