cembeddedstm32microcontrollerembedded-resource

Should interrupts be disabled while communicating with external SPI flash?


I am using an external SPI flash with my STM32 MCU.

I am wondering Can the following scenario lead to data corruption in flash or in the read buffer?

If an ISR triggers at the same time, while the communication (Read/Write/Erase) with flash is ongoing from the main process, and the ISR takes up some clock cycles, then return back to the communication. Can it cause any such issue? How may I go on to investigate it?

Note: ISR doesn't access the SPI bus.


Solution

  • No, you'll be fine. As the master device on the SPI bus, your STM32 generates the clock signal which determines the rate of communication. If something happens to slow down your CPU the only thing you might notice is that there is a longer-than-necessary delay between some transitions on the clock line, but that will not cause any issues with the SPI devices you are communicating with.

    If you're not sure about this, try putting delays of 100 microsecond in lots of different places in your code and see if the SPI communication gets messed up.