verilogsystem-verilogverification

Generating random value for 255 wire bus


I wanted to verify connectivity (using SystemVerilog) of a 255-wire bus from source to destination. To this effect, I wanted to drive random values on the source bus and ensure the corresponding random values reflect on the destination bus.

I would like to know recommended ways to generate 255-wide random numbers. Any suggestions would be helpful.


Solution

  • std::randomize is one way to get random values for such a wide bus. Refer to IEEE Std 1800-2017, section 18.12 Randomization of scope variables—std::randomize()

    module tb;
    
    bit [254:0] bus;
    
    initial begin
        repeat (5) begin
            std::randomize(bus);
            $display("%064h", bus); 
        end
    end
    
    endmodule
    

    Here is an example output:

    9607147fbf764e1c152646c7c54644f552c319e858e97750a61f2e77b2060596
    b0c1f83362c9761cec0ceee12eb5eea317b501ffbc008e110b8794a81e037fd4
    c91f3cd7726ac1aa1d977d1d98e9000ce02a79e27a75641069f56b204f354723
    2333b256ac56fdcf07ac337f31629cebb4a646478cdf40034b5ff2f0bda118f5
    2c1288176ebee1b83d87b3a866667f2f9d7f9014145971c879ba870d8e4fb537