Assignment error: "Cannot assign to array"

I'm fairly new to Verilog and I'm trying to familiarize with it. I'm building an ALU in Verilog, and when I try to assign the value from an operation to the ALU_result reg, I get the error listed above on the title.

parameter N = 8;
input  [N-1:0] inA, inB;
input    [3:0] op;

reg ALU_result[N-1:0] ;

always @(*)
    case(op)
      4'b0000:
        begin
          ALU_result = inA & inB ;
        end
      4'b0001:
        begin
          ALU_result = inA | inB ;
        end  
      4'b0010:
        begin
          ALU_result = inA + inB ;
        end
    endcase

The error I get more specifically. I compiled the Verilog code with icarus verilog.

library.v:39: error: Cannot assign to array ALU_result. Did you forget a word index?
library.v:43: error: Cannot assign to array ALU_result. Did you forget a word index?
library.v:47: error: Cannot assign to array ALU_result. Did you forget a word index?

You declared ALU_result as an unpacked array, but there is no need to do so.

Change:

reg ALU_result[N-1:0] ;

to:

reg [N-1:0] ALU_result;