multidimensional-arraysystem-verilog

SystemVerilog Arrays

Is this array declaration valid?

bit[31:0] shadow_mem[bit[31:0]];

But what does this mean?

We usually declare it as

bit[31:0] shadow_mem[31:0];

Are the two declarations different?
What is the purpose of declaring the second dimension with bit?

Solution

  • This is an associative array declaration with an index type of bit [31:0] I.e. an array with a 32-bit address. It’s not a 32-element array.