simulationsystem-verilogverification

How does a covergroup handle with an event handle sampling when enabling strobe?


I am curious as to how the sampling happens in a SystemVerilog covergroup when we have an event specified and we also use type_option.strobe = 1 for said covergroup. For example:

covergroup c @(posedge clk)
 type_option.strobe=1;

strobe implies sampling happens in the Postponed region, however the @(posedge clk) as an event is evaluated at the Active region. How does the sampling function resolve this?

I tried reading the LRM, but it wasn't very cohesive.


Solution

  • When type_option.strobe = 0, the default, sampling occurs immediately in whatever region the sampling event gets triggered. In some odd cases, that could mean sampling multiple times within the same time slot.

    When type_option.strobe = 1, the sampling event just schedules the actual covergroup sampling to occur once in the postponed region.