Compilation error in Quartus for Verilog language

I am new to Verilog and it's tools. I am simulating/compiling in Quartus Prime. In this particular code, it's showing up an error which is supposed to be the syntax of the language.

Code :

module conditional_op();
    int result;
    int a = 9;
    int b = 31;
    reg c = 0;
    
    initial begin
    
        #1; result = (a == 9) ? 1:0;
        $display("result=%0d",result);
        
        #1; result = ((a+b) == 40) ? 1:0;
        $display("result=%0d",result);
        
        #1; result = (b == 30) ? 678 : -99;
        $display("result=%0d",result);
        
        #1; c = (b ==31)? 1'bz : 1'b0;
        $display("c=%b",c);
    
    end
endmodule

I tried by relocating all the inputs and outputs beside the module name in the parenthesis, but it didn't work.

Your code compiles without errors and simulates as expected on multiple simulators on EDA playground. Here is an example simulation output:

# result=1
# result=1
# result=-99
# c=z

Since you used the int keyword, it is necessary to enable SystemVerilog features in your tool. Refer to the Quartus documentation for doing so. int is a data type that was added to the SystemVerilog extension to the language (IEEE Std 1800). int was not part of the superseded Verilog IEEE Std 1364.

If that still yields compile errors, there may be a bug in the version of the tool you are using. In that case, contact the vendor for support.