How to propagate a value from a Module upwards

I have two modules, one has a latency of x clock cycles, the other one has a latency of y clock cycles. I'd like to tie the latency to each of these modules, so that when I instantiate the module in e.g. a test bench or another module, I can extract the right latency without manually changing x with y each time. This would be the 'inverse' of passing a parameter from the higher module down.

What would be the most Chisel-appropriate way to do this?

I read the latest Chisel book but could not find a solution.

You can simply read a value declared under the module and use it in your code generation.

Here an example on scatie.

import chisel3._
import chisel3.util._

class MyFirstModule extends Module{
    val my_input = IO(Input(UInt(8.W)))
    val my_output = IO(Output(UInt(8.W)))

    val latency = 0

    my_output := my_input
}

class MySecondModule extends Module{
    val my_input = IO(Input(UInt(8.W)))
    val my_output = IO(Output(UInt(8.W)))

    val latency = 1

    my_output := RegNext(my_input)
}

class ConnectModules extends Module{
    val my_input = IO(Input(UInt(8.W)))
    val my_output = IO(Output(UInt(8.W)))

  val my_first_module = Module(new MyFirstModule())
  println(s"Latency of my_first_module is ${my_first_module.latency}")
  my_first_module.my_input := my_input

  val my_second_module = Module(new MySecondModule())
  println(s"Latency of my_second_module is ${my_second_module.latency}")
  my_second_module.my_input := my_first_module.my_output

  my_output := my_second_module.my_output

}

println(getVerilogString(new ConnectModules))

latency is a value declared in Modules that is read by println function in the upwards Module.