I want to use a delay of 5s in my Verilog testbench. However, the time scaling is 1ns/1ps
. I do not want to change this scaling since it effects my clock.
But, how can I write a delay of 5s which is easy to read? Like #5e9
?
#5e9
works on all simulators on EDA playground:
`timescale 1ns/1ps
module tb;
initial begin
#5e9;
$display("Time=%0t", $time);
end
endmodule