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I want to use a delay of 5s in my Verilog testbench. However, the time scaling is 1ns/1ps. I do not want to change this scaling since it effects my clock.

But, how can I write a delay of 5s which is easy to read? Like #5e9?

\n"}}],["$","hr",null,{}],["$","div",null,{"className":"h3","children":["Solution ",["$","li",null,{"className":"h3 fa fa-arrow-down"}]]}],["$","hr",null,{}],["$","$L12",null,{}],["$","div",null,{"dangerouslySetInnerHTML":{"__html":"

#5e9 works on all simulators on EDA playground:

`timescale 1ns/1ps\n\nmodule tb;\n\ninitial begin\n    #5e9;\n    $display("Time=%0t", $time);\nend\n\nendmodule\n

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