I'm trying to recursively instantiate a module in Verilog. The RTL for the module is on my github here.
When I simulate the module using Icarus Verilog, it works properly. However, when I try to use Vivado to synthesize the design, it fails with the following error message:
ERROR: [Synth 8-316] illegal module recursion detected [/home/centos/repos/aws-fpga/hdk/cl/examples/cl_hello_world/build/src_post_encryption/recursive_matrix.v:11]
Before failing, Vivado indicates that it's attempting to instantiate a module like so:
INFO: [Synth 8-6157] synthesizing module 'recursive_matrix' [/home/centos/repos/aws-fpga/hdk/cl/examples/cl_hello_world/build/src_post_encryption/recursive_matrix.v:11]
Parameter N bound to: 0 - type: integer
Parameter NUM_WEIGHTS bound to: 31 - type: integer
Parameter WIRE_DELAY bound to: 32 - type: integer
Parameter NUM_LUTS bound to: 2 - type: integer
Parameter DIAGONAL bound to: 0 - type: integer
Parameter TRANSPOSE bound to: 0 - type: integer
From the code, this should be impossible. It appears that child modules are overriding the value of the N parameter of their parent modules, which behavior that doesn't make much sense to me, nor does it follow the Verilog 2005 spec.
Any idea what's going on here?
I tried using localparams, switching the name of the parameter from N to other names, adding wrapper modules to prevent direct recursion, and switching between treating the files as Verilog2001, Verilog2005, and as SystemVerilog.
I resolved the issue! Apparently, Vivado offers recursion support for Verilog-2005 modules, but not SystemVerilog modules (according to this useful Reddit comment).
It also turns out that if you include a file from a SystemVerilog module, it forces that file to be parsed as SystemVerilog, even if that file was previously included as a Verilog-2005 file. By removing the include statements, I was able to get the module to successfully elaborate!
I hope this helps somebody else running into this weird issue in the future.