[SOLVED] VHDL/GHDL: Why does port name hide entity?

VHDL/GHDL: Why does port name hide entity?

I'm using GHDL v3.0.0 as a VHDL simulator, but I'm getting a warning I don't understand

In short, with this entity:

entity GSR is
    port ( gsr: in std_ulogic);
end GSR;

I get this warning:

mock.vhd:5:16:warning: declaration of "gsr" hides entity "gsr" [-Whide]
        port ( gsr: in std_ulogic);
               ^

Full details... In my simulation I need to mock an entity (so entity name and port names must match the third party library entity I'm mocking).

This is in my mock.vhd file:

library ieee;
use ieee.std_logic_1164.all;

entity GSR is
    port ( gsr: in std_ulogic);
end GSR;

architecture sim of GSR is
begin
end sim;

To show the problem I've created a very cut-down example of a testbench.vhd:

library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
end testbench;

architecture sim of testbench is
    signal resetn : std_logic := '0';
begin
  
  gsr_inst: entity work.GSR port map (gsr => resetn);
  
  process
  begin
    wait;
  end process;
  
end sim;

The warning comes when I analyse:

steven@Stevens-Laptop gsr % ghdl  -a mock.vhd testbench.vhd
mock.vhd:5:16:warning: declaration of "gsr" hides entity "gsr" [-Whide]
        port ( gsr: in std_ulogic);
               ^

I don't see a circumstance where the port gsr can hide the entity GSR, and hence why is this a warning? An example or two of when this could cause a problem would help my understanding.

I think I've described everything that's relevant the problem and what I've done above. I've search for the warning text on-line but found nothing that seems relevant, or maybe I didn't understand it.

Solution

VHDL does not differentiate identifiers by their case:

15.4.2 Basic identifiers

[...] Basic identifiers differing only in the use of corresponding uppercase and lowercase letters are considered the same.

So your port gsr hides the entity GSR.