Can SYSCLK be included in FPGA Xilinx vivado testbenches?

I'm doing a fairly simple design. I have the VC707 FPGA Evaluation Board and from the SYSCLK(P/N) I'm generating a single-ended clock for the rest of the board.

// Differential to single ended buffer for the input System clock of 200 MHz
IBUFGDS #(
    .DIFF_TERM("FALSE"), .IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")
    ) 
IBUFGDS_inst (
    .O(clk),
    .I(SYSCLK_P),
    .IB(SYSCLK_N)
);

This works just fine, but I can't get to simulate the behavior of this clock, since it's an input to the main function. That means I have to define the clock as register in my testbench:

reg SYSCLK:P;
reg SYSCLK_N;

But then I don't know how to proceed from here. I can only simulate a single-ended 200MHz clock:

always
begin
   w_clk = 1'b0;
   forever
      #2.5 w_clk = ~w_clk;
end

I simulated everything, but sadly the SYSCLK stays at not defined in Vivado. If I try assigning it I get the error (concurrent assignment to a non-net 'SYSCLK(P/N)' is not permitted). This is understandable to some sense, but I can't seem to get around it.

EDIT: Adding some additional material upon request:

My main looks something like this:

module main(
    input SYSCLK_P,
    input SYSCLK_N,
    output  [7:0] GPIO_LED
);

IBUFGDS #(
    .DIFF_TERM("FALSE"), .IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")
    ) 
IBUFGDS_inst (
    .O(clk),
    .I(SYSCLK_P),
    .IB(SYSCLK_N)
);

On my FPGA board, the pins (SYSCLK_P & SYSCLK_N) are designated for 200MHz internal clock. I'm using these to supply my main. Now I want to simulate my main on testbench:

module main_tb();


reg SYSCLK_P;
reg SYSCLK_N;

// LEDs on the VC707_FPGA Board itself
wire    [7:0] GPIO_LED;     // LED0..7

main DUT (
.SYSCLK_P(SYSCLK_P),
.SYSCLK_N(SYSCLK_N),

// LEDs on the VC707_FPGA Board itself
.GPIO_LED(GPIO_LED)
);

// 200 MHz master clock
reg w_clk;
always
begin
    w_clk = 1'b0;
    forever
        #2.5 w_clk = ~w_clk;
end

All this is working fine without any errors. I just don't have a signal for SYSCLK, that means I have no driver for my main and nothing is happening. I usually simulate on ModelSim, so I never have to use the on-board clock for simulation. I just create my own clock like here w_clk.. Except this time, I'm simulating with Vivado and this clock is essential for the main, because I'm simulating everything together.

I hope it's understandable now :)

Example TB\w differential driver on SYSCLK_P/N

module tb ();
 
reg SYSCLK_P;
reg SYSCLK_N;
reg w_clk;

// 1) Create testbench clock signal w_clk
// 2) Drive SYSCLK_P/N from w_clk
always
begin
   w_clk = 1'b0;
   forever begin
     // single ended
     #2.5 w_clk = ~w_clk;
     //
     // differential
     SYSCLK_P   =  w_clk;
     SYSCLK_N   = ~w_clk;
   end
end
  
initial begin
  $dumpfile("dump.vcd"); $dumpvars;
  #30;
  $finish;
end
  
endmodule

Produces On edaplayground.com

This should fix the undriven differential clock.

If you drive the inputs of the IBUFGDS and nothing comes out, then you need to compile the unisim libraries to be able to simulate the IBUFGDS model.

If that is the case, then ask or research the question "How to compile the Xilinx unisim libraries for the Vivado simulator". SO already has answers to the this question.