verilogsystem-verilogtest-benchiverilogedaplayground

No .vcd file found error, but I have used the $dump code

I have been trying to open EPWave at EDA playground, and it always returns the error:

No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?

I have added those two at the beginning of the initial, and yet it's not working (also the $finish of course)

This is the project: https://www.edaplayground.com/x/SzkF

I have tried adding time before and after the finish and beginning, naming the dumpfile in another way looking some similar code, but none of that has worked.

Solution

  • iverilog does not always give very useful error messages. Switch to another simulator on EDA Playground. For example, with the Cadence simulator, we get this error message:

      reg[0] b_reg;
       |
xmvlog: *E,SVNPSN (design.sv,132|7): The value in the single-bound form of a range must be positive.
  reg[0] b_reg;
       |
xmvlog: *E,SVPKSN (design.sv,132|7): The single-bound form of a range is only allowed for array (i.e., unpacked) dimensions.

    I can get rid of the compile error when I change:

      reg[0] b_reg;

    to:

      reg b_reg;

    Switching back to iverilog, I no longer see the original VCD error message.