How do i add a "for" loop in VHDL

I'm trying to make this "for" loop work but im stuck with the same error: "Illegal concurrent statement".

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.STD_LOGIC_VECTOR;


entity circ is
    generic ( Width : integer:=8;
          WidthZ : integer:=4);

    port ( z : out std_logic_vector ( WidthZ-1 downto 0 );
           x1 : in std_logic_vector ( Width-1 downto 0 );
           x2 : in std_logic_vector ( Width-1 downto 0 ));
end entity circ;

architecture funcLog_circ of circ is
    signal count : std_logic_vector (3 downto 0);
    begin 
        for i in 0 to 7 loop
            if (x1(i) xor x2(i)) then 
                count <= count + 1;
            end if;
        end loop;
    z <= count;
end architecture;

I really have no clue on why i cannot use the "for" loop.

You need to:

1. Put it in a process
2. Make count a variable as when you iterate across an object in a process without time passing, you need an object that updates immediately
3. If you want count to update every time the process runs, then you need to assign count to 0 at the beginning of the process.
4. Use a type that allows you to add 1, such as unsigned or integer.

    CountItProc : process (X1, X2)
      variable count : unsigned(3 downto 0) ;
    begin 
        count := (others => '0') ;
        for i in 0 to 7 loop
            if (x1(i) xor x2(i)) then 
                count := count + 1;
            end if;
        end loop;
        z <= std_logic_vector(count);
    end process ;